Some example embodiments of inventive concepts relate to a memory device, and more particularly, to a memory device and/or memory system configured to reduce deterioration of a dynamic refresh characteristic caused by a disturbance occurring during access to a memory cell by controlling a refresh operation and/or operating methods thereof.
A high voltage is applied to a word line of a semiconductor memory device, such as a dynamic random access memory (DRAM), to enable a transistor to access a memory cell. However, an electric field generated by the high voltage may decrease a threshold voltage of an access transistor in an adjacent cell. As a result, leakage current of a cell increases, which is called a pass gate effect. In order to prevent data loss due to the leakage current, DRAM requires a refresh operation of reading data from a cell and rewriting the data to the cell before the data stored in the cell is completely lost The refresh operation may be periodically performed in DRAM or may be performed at the request of a system.
Refresh characteristics include a static refresh characteristic and a dynamic refresh characteristic. A time gap between a first refresh operation on a cell in a memory cell array and a second refresh operation on the cell is referred to as a refresh interval.
The static refresh characteristic is the refresh characteristic of a cell when there are a small number of accesses or no accesses to DRAM during the refresh interval. The dynamic refresh characteristic is the refresh characteristic of a cell when there are relatively more accesses to DRAM than in the case of the static refresh characteristic.
A cell is less influenced by an adjacent cell or line and less influenced by power noise occurring when another cell is accessed in a static refresh than in a dynamic refresh. On the contrary, since there are frequent accesses to DRAM in the dynamic refresh, the influence on an adjacent cell varies according to an access frequency. A degree of influence of an access to a cell on each of the other cells in DRAM is referred to as disturbance. When there is a wide gap between cells in a DRAM memory cell array, disturbance is low. However, when the gap between cells is reduced, for example due to scaling, then interference, such as disturbance by an adjacent cell or line, increases.
As for RAM (e.g., DRAM), an access to a particular address cannot be restricted, and therefore, a particular cell may be accessed repeatedly. With the repeated access, the refresh characteristics of the cell rapidly deteriorate due to disturbance.
Therefore, it is beneficial to refresh a cell in which disturbance is concentrated more often in order to improve the refresh characteristics.